000			00569nam a22001577a 4500
999			_c4545 _d4545
008			210507b ||||| |||| 00| 0 eng d
020			_a9781292231167
050			_aTK 7888.3 _b.M36 2019
082			_aTK 7888.3 .M36 2019
100			_9760 _aMano, Morris M., Ciletti, Michael D.
245			_aDigital Design ; _bwith an introduction to the verilog HDL, VHDL, and Systen Verilog _cMano, Morris M., Ciletti, Michael D.
260			_aUK _bPearson _c2019
300			_a710p.
650			_2Building and construction _xSchool of Engineering and Technology
942			_2lcc _cLLB